Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), non-volatile (e.g., flash) memory, dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).
As system speeds have increased, the speed of the clock signals (which are sometimes hereinafter referred to herein as “clocks”) provided to operate memory devices in such systems have increased. Conventionally, such systems operate memory devices with clock signals that have a targeted duty cycle of 50%. As is well known in the art, a clock signal's duty cycle is the percentage of time that the clock signal spends in an active (e.g., high) state relative to the total clock period.
Prior to putting a memory device in operation or in the stream of commerce, it is conventionally tested (e.g., by or for the manufacturer of the memory device or a system including such a memory device, wherein such a system is referred to hereinafter as “the target system”) using a tester that provides the memory device with a clock signal that simulates the clock signal it would be provided in the target system. Ideally, it would be desirable for such testers to provide a clock signal having a duty cycle as close to the target duty cycle (e.g., a 50% duty cycle) as the duty cycle of a clock signal that will be provided in the target system. Unfortunately, conventional volume production testers are incapable of reliably providing such a clock signal, particularly as the speed of such clock signals have increased.
FIG. 1 illustrates a block diagram of an embodiment of a typical prior art memory clock circuit. This circuit can provide a clock for clocking data out of the memory device as well as providing (e.g., coupling, generating, inputting, introducing, etc.) a testing clock for use internal to the memory array.
The clock provided to the memory device (XCLK) is input to an input clock buffer 101 before being input to a delay-locked loop (DLL) 103. The output of the DLL 103 goes through another buffer prior to being input to an output high trim block (tOH) 105. The output high trim block 105 can provide a fixed trim function to remove duty cycle error that has been introduced by memory device components.
The trimmed clock can then be output through a buffer 106 to both a data latch 109 and a clock output buffer 107. The clock can clock data from the memory array 111 into the data latch 109 in order to output the data through a data output buffer 113. The clock can also be output through the clock output buffer 107 as a DQS output strobe, such as to inform external circuits that data is going to be output by the memory device.
A problem can exist when an inaccurate external clock is input to the output high trim block 105 for trimming purposes (e.g., such as a clock provided by a volume production tester). Not only is the external clock inaccurate but the memory device components can introduce additional duty cycle error. The output high trim block 105 would then be set to correct the total duty cycle error as necessary to provide a 50% duty cycle in response to the inaccurate external test clock. Thus, when a more ideal (e.g., 50% duty cycle) clock is again used (e.g., such as a clock provided by the target system for normal operation of the memory device), the output high trim block 105 can introduce an error on the output trimmed clock.